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4 Results:AA:JAE-YOON SIM 0.46 sec.
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1
Circuit Design of DRAM for Mobile Generation
Circuit Design of DRAM for Mobile Generation
Jae-Yoon Sim, | 대한전자공학회 | 2007 ,
2
A Design Guide of 3-stage CMOS Operational Ampifer with Nested Gm-C Frequency Compensation
A Design Guide of 3-stage CMOS Operational Ampifer with Nested Gm-C Frequency Compensation
Jae-Seung Lee, | 대한전자공학회 | 2007 ,
3
A 32mm and 0.9V CMOS Operational Amplifer with Nested Gm-C Frequency Compensation
A 32mm and 0.9V CMOS Operational Amplifer with Nested Gm-C Frequency Compensation
Jae-Seung Lee, | 대한전자공학회 | 2007 ,
4
A 0.12GHz-1.4GHz DLL-based Clock Generator with a Multiplied 4-phase Clock Using a 0.18um CMOS Process
A 0.12GHz-1.4GHz DLL-based Clock Generator with a Multiplied 4-phase Clock Using a 0.18um CMOS Process
Hyung-Joon Chi., | 대한전자공학회 | 2006 ,
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