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A 90-nm FPGA I/O Buffer Design With 1.6-Gb/s Data Rate for Source-Synchronous System and 300-MHz Clock Rate for External Memory Interface
A 90-nm FPGA I/O Buffer Design With 1.6-Gb/s Data Rate for Source-Synchronous System and 300-MHz Clock Rate for External Memory Interface
Tyhach, J, | Institute of Electrical and Electronics Engineers | 2005 ,
2
도서관학 5법칙
도서관학 5법칙
Ranganathan, S. R., 020-R196도 | 한국도서관협회 | 2005 020-R196도,
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