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871
Modeling and Control of Shape Memory Alloy Actuators
Modeling and Control of Shape Memory Alloy Actuators
Jagadeesan Jayender, | Institute of Electrical and Electronics Engineers | 2008 ,
872
A Model Predictive Decentralized Control Scheme With Reduced Communication Requirement for Spacecraft Formation
A Model Predictive Decentralized Control Scheme With Reduced Communication Requirement for Spacecraft Formation
Javad Lavaei, | Institute of Electrical and Electronics Engineers | 2008 ,
873
Optimal Suppression of Laser Beam Jitter by High-Order RLS Adaptive Control
Optimal Suppression of Laser Beam Jitter by High-Order RLS Adaptive Control
Pawel K. Orzechowski, | Institute of Electrical and Electronics Engineers | 2008 ,
874
Active Vibration Isolation Using an Electrical Damper or an Electrical Dynamic Absorber
Active Vibration Isolation Using an Electrical Damper or an Electrical Dynamic Absorber
Sang-Myeong Kim, | Institute of Electrical and Electronics Engineers | 2008 ,
875
Invariance-Preserving Abstractions of Hybrid Systems: Application to User Interface Design
Invariance-Preserving Abstractions of Hybrid Systems: Application to User Interface Design
Meeko Oishi, | Institute of Electrical and Electronics Engineers | 2008 ,
876
Output Feedback Controller for Operation of Spark Ignition Engines at Lean Conditions Using Neural Networks
Output Feedback Controller for Operation of Spark Ignition Engines at Lean Conditions Using Neural Networks
Jonathan Blake Vance, | Institute of Electrical and Electronics Engineers | 2008 ,
877
Augmented Hamiltonian Formulation and Energy-Based Control Design of Uncertain Mechanical Systems
Augmented Hamiltonian Formulation and Energy-Based Control Design of Uncertain Mechanical Systems
Yuzhen Wang, | Institute of Electrical and Electronics Engineers | 2008 ,
878
Suboptimal Control of Switched Systems With an Application to the DISC Engine
Suboptimal Control of Switched Systems With an Application to the DISC Engine
Michael Rinehart, | Institute of Electrical and Electronics Engineers | 2008 ,
879
A 90-nm FPGA I/O Buffer Design With 1.6-Gb/s Data Rate for Source-Synchronous System and 300-MHz Clock Rate for External Memory Interface
A 90-nm FPGA I/O Buffer Design With 1.6-Gb/s Data Rate for Source-Synchronous System and 300-MHz Clock Rate for External Memory Interface
Tyhach, J, | Institute of Electrical and Electronics Engineers | 2005 ,
880
A Baseband Processor for Impulse Ultra-Wideband Communications
A Baseband Processor for Impulse Ultra-Wideband Communications
Blazquez, R, | Institute of Electrical and Electronics Engineers | 2005 ,
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