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저 전력 Folding- Interpolation 기법을 적용한 1.8V 6-bit 100MS/s 5mW CMOS A/D 변화기의 설계
저 전력 Folding- Interpolation 기법을 적용한 1.8V 6-bit 100MS/s 5mW CMOS A/D 변화기의 설계
문준호, | 대한전자공학회 | 2006 ,
2
Folding Anaysis of Reversal Arch by the Tangent Stiffness Method
Folding Anaysis of Reversal Arch by the Tangent Stiffness Method
Shin-ichi Iguchi, Shigeo Goto, Katsushi Ijima and, | 국제구조공학회 | 2001 ,
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