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A 90-nm FPGA I/O Buffer Design With 1.6-Gb/s Data Rate for Source-Synchronous System and 300-MHz Clock Rate for External Memory Interface
A 90-nm FPGA I/O Buffer Design With 1.6-Gb/s Data Rate for Source-Synchronous System and 300-MHz Clock Rate for External Memory Interface
Detailed Information
- 자료유형
- 기사
- ISSN
- 00189200
- 저자명
- Tyhach, J
- 서명/저자
- A 90-nm FPGA I/O Buffer Design With 1.6-Gb/s Data Rate for Source-Synchronous System and 300-MHz Clock Rate for External Memory Interface / Tyhach, J , 공저 Wang, B. , Sung, C. , uang, J. , Nguyen, K. , Wang, X. , Chong, Y. , Pan, P. , Kim, H. , Rangan, G.
- 발행사항
- New York : Institute of Electrical and Electronics Engineers, 2005.
- 형태사항
- pp. 1829-1838
- 주기사항
- 참고문헌 수록
- 기타저자
- Wang, B.
- 기타저자
- Sung, C.
- 기타저자
- uang, J.
- 기타저자
- Nguyen, K.
- 기타저자
- Wang, X.
- 기타저자
- Chong, Y.
- 기타저자
- Pan, P.
- 기타저자
- Kim, H.
- 기타저자
- Rangan, G.
- 원문정보
- url
- 모체레코드
- 모체정보확인
- Control Number
- kjul:60234035
MARC
008191007s2005 us aa eng■022 ▼a00189200
■1001 ▼aTyhach, J
■24510▼aA 90-nm FPGA I/O Buffer Design With 1.6-Gb/s Data Rate for Source-Synchronous System and 300-MHz Clock Rate for External Memory Interface▼dTyhach, J▼e공저 Wang, B.▼eSung, C.▼euang, J.▼eNguyen, K.▼eWang, X.▼eChong, Y.▼ePan, P.▼eKim, H.▼eRangan, G.
■260 ▼aNew York▼bInstitute of Electrical and Electronics Engineers▼c2005.
■300 ▼app. 1829-1838
■500 ▼a참고문헌 수록
■7001 ▼aWang, B.
■7001 ▼aSung, C.
■7001 ▼auang, J.
■7001 ▼aNguyen, K.
■7001 ▼aWang, X.
■7001 ▼aChong, Y.
■7001 ▼aPan, P.
■7001 ▼aKim, H.
■7001 ▼aRangan, G.
■773 ▼tIEEE journal of solid-state circuits▼gVol.40 No.9 (SEPTEMBER)▼d2005, 09
■856 ▼uhttp://sscs.ieee.org/
■SIS ▼aS074570▼b60229100▼h8▼s2▼fP
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