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Design and Implementation of an Embedded 512-KB Level-2 Cache Subsystem
Design and Implementation of an Embedded 512-KB Level-2 Cache Subsystem
Detailed Information
- 자료유형
- 기사
- ISSN
- 00189200
- 저자명
- Shin, J. L
- 서명/저자
- Design and Implementation of an Embedded 512-KB Level-2 Cache Subsystem / Shin, J. L , 공저 Petrick, B. , Singh, M. , Leon, A. S.
- 발행사항
- New York : Institute of Electrical and Electronics Engineers, 2005.
- 형태사항
- pp. 1815-1820
- 주기사항
- 참고문헌 수록
- 기타저자
- Petrick, B.
- 기타저자
- Singh, M.
- 기타저자
- Leon, A. S.
- 원문정보
- url
- 모체레코드
- 모체정보확인
- Control Number
- kjul:60234033
MARC
008191007s2005 us aa eng■022 ▼a00189200
■1001 ▼aShin, J. L
■24510▼aDesign and Implementation of an Embedded 512-KB Level-2 Cache Subsystem▼dShin, J. L▼e공저 Petrick, B.▼eSingh, M.▼eLeon, A. S.
■260 ▼aNew York▼bInstitute of Electrical and Electronics Engineers▼c2005.
■300 ▼app. 1815-1820
■500 ▼a참고문헌 수록
■7001 ▼aPetrick, B.
■7001 ▼aSingh, M.
■7001 ▼aLeon, A. S.
■773 ▼tIEEE journal of solid-state circuits▼gVol.40 No.9 (SEPTEMBER)▼d2005, 09
■856 ▼uhttp://sscs.ieee.org/
■SIS ▼aS074570▼b60229100▼h8▼s2▼fP
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