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Process Variation in Embedded Memories: Failure Analysis and Variation Aware Architecture
Process Variation in Embedded Memories: Failure Analysis and Variation Aware Architecture
Detailed Information
- 자료유형
- 기사
- ISSN
- 00189200
- 저자명
- Agarwal, A
- 서명/저자
- Process Variation in Embedded Memories: Failure Analysis and Variation Aware Architecture / Agarwal, A , 공저 Paul, B. C. , Mukhopadhyay, S. , Roy, K.
- 발행사항
- New York : Institute of Electrical and Electronics Engineers, 2005.
- 형태사항
- pp. 1804-1814
- 주기사항
- 참고문헌 수록
- 기타저자
- Paul, B. C.
- 기타저자
- Mukhopadhyay, S.
- 기타저자
- Roy, K.
- 원문정보
- url
- 모체레코드
- 모체정보확인
- Control Number
- kjul:60234032
MARC
008191007s2005 us aa eng■022 ▼a00189200
■1001 ▼aAgarwal, A
■24510▼aProcess Variation in Embedded Memories: Failure Analysis and Variation Aware Architecture▼dAgarwal, A▼e공저 Paul, B. C.▼eMukhopadhyay, S.▼eRoy, K.
■260 ▼aNew York▼bInstitute of Electrical and Electronics Engineers▼c2005.
■300 ▼app. 1804-1814
■500 ▼a참고문헌 수록
■7001 ▼aPaul, B. C.
■7001 ▼aMukhopadhyay, S.
■7001 ▼aRoy, K.
■773 ▼tIEEE journal of solid-state circuits▼gVol.40 No.9 (SEPTEMBER)▼d2005, 09
■856 ▼uhttp://sscs.ieee.org/
■SIS ▼aS074570▼b60229100▼h8▼s2▼fP
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