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Analog CMOS Performance Degradation due to Edge Direct Tunnelling(EDT) Current in sub-100nm Technology
Analog CMOS Performance Degradation due to Edge Direct Tunnelling(EDT) Current in sub-100nm Technology
Detailed Information
- 자료유형
- 기사
- ISSN
- 15981657
- 저자명
- Navakanta Bhat
- 서명/저자
- Analog CMOS Performance Degradation due to Edge Direct Tunnelling(EDT) Current in sub-100nm Technology / Navakanta Bhat , 공저 Chandrabhan Sigh Thakur
- 발행사항
- 서울 : 대한전자공학회, 2003.
- 형태사항
- pp. 139-144
- 주기사항
- 참고문헌 수록
- 기본자료저록
- Journal of Semiconductor Technology and Science : Volume 3, Number 3, (2003 September) 2003, 09
- 원문정보
- url
- 모체레코드
- 모체정보확인
- Control Number
- kjul:60202500
MARC
008190108s2003 ulk aa eng■022 ▼a15981657
■1001 ▼aNavakanta Bhat
■24510▼aAnalog CMOS Performance Degradation due to Edge Direct Tunnelling(EDT) Current in sub-100nm Technology▼dNavakanta Bhat▼e공저 Chandrabhan Sigh Thakur
■260 ▼a서울▼b대한전자공학회▼c2003.
■300 ▼app. 139-144
■500 ▼a참고문헌 수록
■7001 ▼aChandrabhan Sigh Thakur
■773 ▼tJournal of Semiconductor Technology and Science▼gVolume 3, Number 3, (2003 September)▼d2003, 09
■856 ▼ahttp://www.jsts.org
■SIS ▼aS013699▼b60054120▼h8▼s2▼fP
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