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A Pipelined Hardware Architecture of an H.264 Deblocking Filter with an Efficient Data Distribution
A Pipelined Hardware Architecture of an H.264 Deblocking Filter with an Efficient Data Distribution
Detailed Information
- 자료유형
- 기사
- ISSN
- 15981657
- 저자명
- Sang-Heon Lee.
- 서명/저자
- A Pipelined Hardware Architecture of an H.264 Deblocking Filter with an Efficient Data Distribution / Sang-Heon Lee. , Hyuk-Jae Lee
- 발행사항
- 서울 : 대한전자공학회, 2006.
- 형태사항
- pp. 227-233
- 기타저자
- Hyuk-Jae Lee
- 기본자료저록
- Journal of Semiconductor Technology and Science : Volume 6, Number 4, (2006 December) 2006, 12
- 모체레코드
- 모체정보확인
- Control Number
- kjul:60094058
MARC
008070320s2006 ULKa a ENG■022 ▼a15981657
■1001 ▼aSang-Heon Lee.
■245 ▼aA Pipelined Hardware Architecture of an H.264 Deblocking Filter with an Efficient Data Distribution▼dSang-Heon Lee.▼eHyuk-Jae Lee
■260 ▼a서울▼b대한전자공학회▼c2006.
■300 ▼app. 227-233
■653 ▼aPIPELINED▼aHARDWARE▼aARCHITECTURE▼aH.264▼aDEBLOCKING▼aFILTER▼aEFFICIENT▼aDATA▼aDISTRIBUTION
■7001 ▼aHyuk-Jae Lee
■773 ▼tJournal of Semiconductor Technology and Science▼gVolume 6, Number 4, (2006 December)▼d2006, 12
■SIS ▼aS037327▼b60054120▼h8▼s2
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