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Evolution of Interface Voids under Current and Temperature Stress in Integrate Circuit Metallization
Evolution of Interface Voids under Current and Temperature Stress in Integrate Circuit Metallization
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MARC
008050913s2004 ULKa a ENG■022 ▼a12259438
■245 ▼aEvolution of Interface Voids under Current and Temperature Stress in Integrate Circuit Metallization▼d공저 J.H. Choy, K.L. Kavanagh, Y.C. Kim
■260 ▼a서울▼b대한금속.재료학회▼c2004.
■300 ▼app. 411-416
■653 ▼aEVOLUTION▼aINTERFACE▼aVOIDS▼aCURRENT▼aTEMPERATURE▼aSTRESS▼aINTEGRATE▼aCIRCUIT▼aMETALLIZATION
■700 ▼aJ.H. Choy, K.L. Kavanagh, Y.C. Kim
■773 ▼tMetals and Materials▼gVOL.10 NO.5 (2004 OCTOBER)▼d2004, 10
■SIS ▼aS010856▼b60013551▼h1▼s2▼fP
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