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Introductory VHDL : from simulation to synthesis
Introductory VHDL : from simulation to synthesis
Detailed Information
- 자료유형
- 단행본
- ISBN
- 0130809829
- ISBN
- 0130899232
- 청구기호
- 566 Y16i
- 서명/저자
- Introductory VHDL : from simulation to synthesis / Sudhakar Yalamanchili.
- 발행사항
- Upper Saddle River, NJ : Prentice Hall, c2001.
- 형태사항
- xix, 401 p. : ill. ; 24cm+2computer optical disc (4 3/4 in)
- 총서명
- Prentice Hall Xilinx design series
- 서지주기
- Includes bibliographical references and index.
- 가격
- 26000
- Control Number
- kjul:60037586
MARC
008050117s2001 njua b 001 0 eng■020 ▼a0130809829
■020 ▼a0130899232
■035 ▼aKRIC07929990
■090 ▼a566▼bY16i
■1001 ▼aYalamanchili, Sudhakar.
■24510▼aIntroductory VHDL▼bfrom simulation to synthesis▼dSudhakar Yalamanchili.
■260 ▼aUpper Saddle River, NJ▼bPrentice Hall▼cc2001.
■300 ▼axix, 401 p.▼bill.▼c24cm▼e2computer optical disc (4 3/4 in)
■44000▼aPrentice Hall Xilinx design series
■504 ▼aIncludes bibliographical references and index.
■650 0▼aVHDL (Computer hardware description language)
■9500 ▼b26000
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