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VLSI chip design with the hareware decription language VERILOG and introduction based on a large RISC processor design
VLSI chip design with the hareware decription language VERILOG and introduction based on a large RISC processor design
상세정보
- 자료유형
- 단행본
- ISBN
- 3540600329
- 청구기호
- 569.47 G629v
- 저자명
- Golze, Ulruch
- 서명/저자
- VLSI chip design with the hareware decription language VERILOG and introduction based on a large RISC processor design / Ulruch Golze.
- 발행사항
- Berlin : Springer-verlag, 1996.
- 형태사항
- xiv, 358 p. : illus. ; 23 cm.
- 서지주기
- includes bibliographical reference and index.
- 가격
- 22000
- Control Number
- kjul:50027338
MARC
008010918s1996 gw a 001 eng■020 ▼a3540600329
■090 ▼a569.47▼bG629v
■1001 ▼aGolze, Ulruch
■24510▼aVLSI chip design with the hareware decription language VERILOG and introduction based on a large RISC processor design▼dUlruch Golze.
■260 ▼aBerlin▼bSpringer-verlag▼c1996.
■300 ▼axiv, 358 p.▼billus.▼c23 cm.
■504 ▼aincludes bibliographical reference and index.
■9500 ▼b22000
