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Quick-turnaround asic design in VHDL : core-based behavioral synthesis
Quick-turnaround asic design in VHDL : core-based behavioral synthesis
Detailed Information
- 자료유형
- 단행본
- 청구기호
- 567.013 R762q
- 서명/저자
- Quick-turnaround asic design in VHDL : core-based behavioral synthesis / Mohamed S. Ben Romdhane , Vijay K. Madisetti , John W. Hines.
- 발행사항
- Boston : Kluwer Academic Publishers, c1996.
- 형태사항
- xviii, 180 p. : ill. ; 25 cm.
- 총서명
- Kluwer international series in engineering and computer science: VLSI, computer architecture, and digital signal processing ; v. 367
- 서지주기
- includes bibliographical references and index.
- 기타저자
- Hines, John W.
- 기타저자
- Madisetti, Vijay K.
- 가격
- 20000
- Control Number
- kjul:50027237
MARC
008010911s1996 us a 001 eng■005 20010911163811.0
■035 ▼aKRIC00210130
■090 ▼a567.013▼bR762q
■1001 ▼aRomdhane, Mohamed S. Ben
■24510▼aQuick-turnaround asic design in VHDL▼bcore-based behavioral synthesis▼dMohamed S. Ben Romdhane▼eVijay K. Madisetti▼eJohn W. Hines.
■260 ▼aBoston▼bKluwer Academic Publishers▼cc1996.
■300 ▼axviii, 180 p.▼bill.▼c25 cm.
■49010▼aKluwer international series in engineering and computer science: VLSI, computer architecture, and digital signal processing▼vv. 367
■504 ▼aincludes bibliographical references and index.
■7001 ▼aHines, John W.
■7001 ▼aMadisetti, Vijay K.
■9500 ▼b20000
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