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Reduced instruction set computer architectures for VLSI
Reduced instruction set computer architectures for VLSI
Detailed Information
- 자료유형
- 단행본
- ISBN
- 0262111039
- 청구기호
- 566.36 K19r
- 서명/저자
- Reduced instruction set computer architectures for VLSI / Manolis G. H. Katevenis.
- 발행사항
- London : The MIT Press, 1985.
- 형태사항
- 215 p. : illus. ; 24 cm.
- 총서명
- ACM doctoral dissertation award ; 1984
- 주기사항
- Orginally presented as author's thesis (Ph.D.) University of California, Berkeley, 1983.
- 학위논문주기
- includes bibliographical references and index.
- 가격
- 26000
- Control Number
- kjul:50027135
MARC
008010911s1985 us a 000 eng■005 20010911160021.0
■020 ▼a0262111039
■035 ▼aKRIC00397837
■090 ▼a566.36▼bK19r
■1001 ▼aKatevenis, Manolis G. H.
■24510▼aReduced instruction set computer architectures for VLSI▼dManolis G. H. Katevenis.
■260 ▼aLondon▼bThe MIT Press▼c1985.
■300 ▼a215 p.▼billus.▼c24 cm.
■49010▼aACM doctoral dissertation award▼v1984
■50000▼aOrginally presented as author's thesis (Ph.D.) University of California, Berkeley, 1983.
■5020 ▼aincludes bibliographical references and index.
■9500 ▼b26000
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| Reg No. | Количество платежных | Местоположение | статус | Ленд информации |
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