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Switch-level timing simulation of MOS VLSI circuits
Switch-level timing simulation of MOS VLSI circuits
Detailed Information
- 자료유형
- 단행본
- ISBN
- 0898383021
- 청구기호
- 569.8 R215s
- 저자명
- Rao, Vasant B.
- 서명/저자
- Switch-level timing simulation of MOS VLSI circuits / Vasant B. Rao , David V. Overhauser , Timothy N. Trick...[et al.].
- 발행사항
- Boston : Kluwer Academic Publishers, 1989.
- 형태사항
- 209 p. : illus ; 23 cm.
- 서지주기
- Includes index.
- 기타저자
- Overhauser, David V.
- 기타저자
- Trick., Timothy N.
- 가격
- 42000
- Control Number
- kjul:50026661
MARC
008010917s1989 us a 001 eng■005 20010917141159.0
■020 ▼a0898383021
■035 ▼aKRIC00389919
■090 ▼a569.8▼bR215s
■1001 ▼aRao, Vasant B.
■24510▼aSwitch-level timing simulation of MOS VLSI circuits▼dVasant B. Rao▼eDavid V. Overhauser▼eTimothy N. Trick...[et al.].
■260 ▼aBoston▼bKluwer Academic Publishers▼c1989.
■300 ▼a209 p.▼billus▼c23 cm.
■504 ▼aIncludes index.
■7001 ▼aOverhauser, David V.
■7001 ▼aTrick., Timothy N.
■9500 ▼b42000
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| Reg No. | Количество платежных | Местоположение | статус | Ленд информации |
|---|---|---|---|---|
| W026118 | 569.8 R215s c.2 | 서양서제2서고 | 대출가능 |
대출가능 My Folder 부재도서신고 |
| W026661 | 569.8 R215s | 서양서제2서고 | 대출가능 |
대출가능 My Folder 부재도서신고 |
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