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Logic synthesis and verification algorithms
Logic synthesis and verification algorithms / Gary D. hachtel , Fabio Somenzi.
Logic synthesis and verification algorithms

Detailed Information

자료유형  
 단행본
청구기호  
566.36 H117l
저자명  
hachtel, Gary D.
서명/저자  
Logic synthesis and verification algorithms / Gary D. hachtel , Fabio Somenzi.
발행사항  
Mass. : Kluwer Academic Publishers, 1996.
형태사항  
xxxi, 564 p. : ill. ; 25 cm.
서지주기  
includes index and bibliographical references
기타저자  
Somenzi, Fabio
가격  
42000
Control Number  
kjul:50026501

MARC

 008010917s1996        us  a                    001      eng
■005    20010917103031.0
■035    ▼aKRIC01774674
■090    ▼a566.36▼bH117l
■1001  ▼ahachtel,  Gary  D.
■24510▼aLogic  synthesis  and  verification  algorithms▼dGary  D.  hachtel▼eFabio  Somenzi.
■260    ▼aMass.▼bKluwer  Academic  Publishers▼c1996.
■300    ▼axxxi,  564  p.▼bill.▼c25  cm.
■504    ▼aincludes  index  and  bibliographical  references
■7001  ▼aSomenzi,  Fabio
■9500  ▼b42000

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